As is well known, an antifuse cell is one kind of one time programmable cell (also referred as an OTP cell). The antifuse cell comprises an antifuse transistor. If the voltage difference between the gate terminal and the source/drain terminal of the antifuse transistor is not higher than the withstanding voltage, the antifuse transistor is in a high-resistance state. Whereas, if the voltage difference between the gate terminal and the source/drain terminal of the antifuse transistor is higher than the withstanding voltage, the gate oxide layer of the antifuse transistor is ruptured and the antifuse transistor is in a low-resistance state.
Moreover, U.S. Pat. No. 9,613,714 disclosed an OTP cell that is able to generate a random code. FIG. 1A is a schematic equivalent circuit diagram illustrating a conventional antifuse differential cell for generating a random code. FIG. 1B is a bias voltage table illustrating the bias voltages for programming and reading the conventional antifuse differential cell of FIG. 1A.
As shown in FIG. 1A, the antifuse differential cell c1 comprises a first select transistor S1, a first antifuse transistor A1, an isolation transistor O, a second antifuse transistor A2 and a second select transistor S2, which are serially connected between a bit line BL and an inverted bit line BLB. The gate terminal of the first select transistor S1 is connected with a word line WL. The gate terminal of the first antifuse transistor A1 is connected with a first antifuse control line AF1. The gate terminal of the isolation transistor O is connected with an isolation control line IG. The gate terminal of the second antifuse transistor A2 is connected with a second antifuse control line AF2. The gate terminal of the second select transistor S2 is connected with the word line WL.
Please refer to FIG. 1B. During a program cycle, a ground voltage (0V) is provided to the bit line BL and the inverted bit line BLB, a select voltage Vdd is provided to the word line WL, a program voltage Vpp is provided to the first antifuse control line AF1 and the second antifuse control line AF2, and an on voltage Von is provided to the isolation control line IG.
During the program cycle, all of the first select transistor S1, the second select transistor S2 and the isolation transistor O are turned on and the state of one of the first antifuse transistor A1 and the second antifuse transistor A2 is changed. For example, the first antifuse transistor A1 is changed to the low-resistance state, but the second antifuse transistor A2 is maintained in the high-resistance state. Alternatively, the second antifuse transistor A2 is changed to the low-resistance state, but the first antifuse transistor A1 is maintained in the high-resistance state.
During a read cycle, the ground voltage (0V) is provided to the bit line BL and the inverted bit line BLB, the select voltage Vdd is provided to the word line WL, a read voltage Vr is provided to the first antifuse control line AF1 and the second antifuse control line AF2, and an off voltage Voff is provided to the isolation control line IG.
During the read cycle, the first select transistor S1 and the second select transistor S2 are turned on, and the isolation transistor O is turned off. The first antifuse transistor A1 and the second antifuse transistor A2 generate read currents to the bit line BL and the inverted bit line BLB. Generally, the read current generated by the antifuse transistor with the low-resistance state is higher, and the read current generated by the antifuse transistor with the high-resistance state is lower. For example, the read current generated by the antifuse transistor with the low-resistance state is 10 μA, and the read current generated by the antifuse transistor with the high-resistance state is 0.1 μA.
During the read cycle, a processing circuit (not shown) determines the storage state of the antifuse differential cell c1 according to the magnitudes of the read currents from first antifuse transistor A1 and the second antifuse transistor A2. In case that the read current generated by the first antifuse transistor A1 is higher and the read current generated by the second antifuse transistor A2 is lower, the antifuse differential cell c1 is verified to have a first storage state. In case that the read current generated by the first antifuse transistor A1 is lower and the read current generated by the second antifuse transistor A2 is higher, the antifuse differential cell c1 is verified to have a second storage state. Due to the manufacturing variations of the antifuse transistors A1 and A2, it is unable to realize which of the antifuse transistors A1 and A2 has the changed state while the reading action is performed. After the antifuse differential cell c1 is programmed, the storage state of the antifuse differential cell c1 is used as a bit of a random code. For example, the eight storage states of the eight programmed antifuse differential cells indicate a one-byte random code.
FIG. 2A is a schematic equivalent circuit diagram illustrating another conventional antifuse differential cell for generating a random code. FIG. 2B is a bias voltage table illustrating the bias voltages for programming and reading the conventional antifuse differential cell of FIG. 2A.
As shown in FIG. 2A, the antifuse differential cell c2 comprises a first antifuse transistor A1, an isolation transistor O and a second antifuse transistor A2, which are serially connected between a bit line BL and an inverted bit line BLB. The gate terminal of the first antifuse transistor A1 is connected with a first antifuse control line AF1. The gate terminal of the isolation transistor O is connected with an isolation control line IG. The gate terminal of the second antifuse transistor A2 is connected with a second antifuse control line AF2.
The gate oxide layer of the first antifuse transistor A1 comprises a first part and a second part. In the first antifuse transistor A1, the first part of the gate oxide layer is closer to the isolation transistor O, and the second part of the gate oxide layer is closer to the bit line BL. The first part of the gate oxide layer is thinner than the second part of the gate oxide layer. Similarly, the second antifuse transistor A2 comprises a first part and a second part. In the second antifuse transistor A2, the first part of the gate oxide layer is closer to the isolation transistor O, and the second part of the gate oxide layer is closer to the inverted bit line BLB. The first part of the gate oxide layer is thinner than the second part of the gate oxide layer.
Please refer to FIG. 2B. During program cycle, a ground voltage (0V) is provided to the bit line BL and the inverted bit line BLB, a program voltage Vpp is provided to the first antifuse control line AF1 and the second antifuse control line AF2, and an on voltage Von is provided to the isolation line IG.
During the program cycle, the storing state of one the first antifuse transistor A1 or the second antifuse transistor A2 is changed. For example, in case that the first part of the gate oxide layer of the first antifuse transistor A1 is ruptured and the first antifuse transistor A1 is changed to the low-resistance state, the second antifuse transistor A2 is maintained in the high-resistance state. Alternatively, in case that the first part of the gate oxide layer of the second antifuse transistor A2 is ruptured and the second antifuse transistor A2 is changed to the low-resistance state, the first antifuse transistor A1 is maintained in the high-resistance state.
During a read cycle, the ground voltage (0V) is provided to the bit line BL and the inverted bit line BLB, a read voltage Vr is provided to the first antifuse control line AF1 and the second antifuse control line AF2, and an off voltage Voff is provided to the isolation control line IG. Consequently, the first antifuse transistor A1 and the second antifuse transistor A2 generate read currents to the bit line BL and the inverted bit line BLB. Subsequently, a processing circuit (not shown) determines the storage state of the antifuse differential cell c2 according to the magnitudes of the read currents from first antifuse transistor A1 and the second antifuse transistor A2.
Due to the manufacturing variations of the antifuse transistors A1 and A2, it is unable to realize which of the antifuse transistors A1 and A2 has the changed state while the reading action is performed. After the antifuse differential cell c2 is programmed, the storage state of the antifuse differential cell c2 is used as a bit of a random code.
FIG. 3A is a schematic equivalent circuit diagram illustrating another conventional antifuse differential cell for generating a random code. FIG. 3B is a bias voltage table illustrating the bias voltages for programming and reading the conventional antifuse differential cell of FIG. 3A.
As shown in FIG. 3A, the antifuse differential cell c3 comprises a first select transistor S1, a first switch transistor W1, a first antifuse transistor A1, an isolation transistor O, a second antifuse transistor A2, a second switch transistor W2 and a second select transistor S2, which are serially connected between a bit line BL and an inverted bit line BLB.
The gate terminal of the first select transistor S1 is connected with a word line WL. The gate terminal of the first switch transistor W1 is connected with a switch control line SW. The gate terminal of the first antifuse transistor A1 is connected with a first antifuse control line AF1. The gate terminal of the isolation transistor O is connected with an isolation control line IG. The gate terminal of the second antifuse transistor A2 is connected with a second antifuse control line AF2. The gate terminal of the second switch transistor W2 is connected with a switch control line SW. The gate terminal of the second select transistor S2 is connected with the word line WL.
Please refer to FIG. 3B. During a program cycle, a ground voltage (0V) is provided to the bit line BL and the inverted bit line BLB, a select voltage Vdd is provided to the word line WL, a switch voltage Vsw is provided to the switch control line SW, a program voltage Vpp is provided to the first antifuse control line AF1 and the second antifuse control line AF2, and an on voltage Von is provided to the isolation control line IG.
During the program cycle, all of the first select transistor S1, the second select transistor S2, the first switch transistor W1, the second switch transistor W2 and the isolation transistor O are turned on and the state of one of the first antifuse transistor A1 and the second antifuse transistor A2 is changed. For example, the first antifuse transistor A1 is changed to the low-resistance state, but the second antifuse transistor A2 is maintained in the high-resistance state. Alternatively, the second antifuse transistor A2 is changed to the low-resistance state, but the first antifuse transistor A1 is maintained in the high-resistance state.
During a read cycle, the ground voltage (0V) is provided to the bit line BL and the inverted bit line BLB, the select voltage Vdd is provided to the word line WL, the switch voltage Vsw is provided to the switch control line SW, a read voltage Vr is provided to the first antifuse control line AF1 and the second antifuse control line AF2, and an off voltage Voff is provided to the isolation control line IG.
During the read cycle, the first select transistor S1, the second select transistor S2, the first switch transistor W1 and the second switch transistor W2 are turned on, and the isolation transistor O is turned off. The first antifuse transistor A1 and the second antifuse transistor A2 generate read currents to the bit line BL and the inverted bit line BLB. Subsequently, a processing circuit (not shown) determines the storage state of the antifuse differential cell c3 according to the magnitudes of the read currents from first antifuse transistor A1 and the second antifuse transistor A2.
Due to the manufacturing variations of the antifuse transistors A1 and A2, it is unable to realize which of the antifuse transistors A1 and A2 has the changed state while the reading action is performed. After the antifuse differential cell c3 is programmed, the storage state of the antifuse differential cell c3 is used as a bit of a random code.
Ideally, during the program cycle of the antifuse differential cell, the gate oxide layer of only one antifuse transistor is ruptured and the state is changed. Whereas, the gate oxide layer of the other antifuse transistor is not ruptured, and the state is not changed.
However, in some situations, the gate oxide layers of the two antifuse transistors are ruptured during the program cycle of the antifuse differential cell. Correspondingly, during the read cycle, the read currents generated by the two antifuse transistors of the antifuse differential cell are very large. Under this circumstance, the processing circuit cannot accurately judge the storage state of the antifuse differential cell.